1. Field of the Invention
The present invention relates to the testing of integrated circuits. More particularly, the present invention relates to identifying the cause of yield loss in the integrated circuit manufacturing process.
2. The Prior Art
Integrated circuits have become the dominant form for the expression of electronic functions because of their ability to provide extensive functionality at moderate cost. Basic to the cost structure of modern integrated circuit (IC) technology is achieving high yields in the manufacturing process. A dominant yield-limiting factor, especially for digital circuits, is random fabrication defects.
Methods for identifying regions in which defects can cause failure-inducing faults, sometimes referred to as critical areas, from IC layouts are well known to those in the IC testing art. Such methods are discussed in Maly et al, xe2x80x9cSystematic Characterization of Physical Defects for Fault Analysis of MOS IC Cellsxe2x80x9d, 1984 IEEE International Test Conference, pp.390-399; Ferguson et al, xe2x80x9cA CMOS Fault Extractor for Inductive Fault Analysisxe2x80x9d, IEEE Trans. on CAD, vol. 7, No. 11 Nov. 1988, pp. 1181-94; A. Jee and F. J. Ferguson, xe2x80x9cCarafe: An Inductive Fault Analysis Tool for CMOS VLSI Circuitsxe2x80x9d, Proceedings of the 11th VLSI Test Symposium, 1993, pp. 92-8; and Charles H. Stapper and Raymond J. Rosner, xe2x80x9cIntegrated Circuit Yield Management and Yield Analysis: Development and Implementationxe2x80x9d, IEEE Trans. on Semiconductor Manufacturing, Vol. 8, pp. 95-102 (1995).
There have also been efforts to predict the yield of integrated circuits. See, for example, U.S. Pat. No. 3,751,647 to Maeder et al., xe2x80x9cSemiconductor and Integrated Circuit Device Yield Modelingxe2x80x9d; U.S. Pat. No. 5,777,901 to Berezin et al. xe2x80x9cMethod and System for Automated Die Yield Prediction in Semiconductor Manufacturingxe2x80x9d; U.S. Pat. No. 5,777,901 to Moosa et al., xe2x80x9cSystems, Methods, and Computer Program Products for Prediction of Defect-Related Failures in Integrated Circuitsxe2x80x9d.
Finally, there have been efforts at diagnosing the causes of the failures of individual ICs from electrical test results. See, for example, U.S. Pat. No. 5,475,695 to Caywood et al, xe2x80x9cAutomatic Failure Analysis Systemxe2x80x9d; U.S. Pat. No. 5,808,919 to Priest et al., xe2x80x9cDiagnostic Systemxe2x80x9d; T. Tsujide et al, xe2x80x9cAutomatic Memory Failure Analysis Using an Expert System in Conjunction with a Memory Tester/Analyzerxe2x80x9d, International Reliability Physics Symp. PP. 184-9 (1993); D. Y. Lepejian, et al, xe2x80x9cAn Automated Failure Analysis (AFA) Methodology for Repeated Structuresxe2x80x9d, 12th IEEE VLSI Test Symp. (1994); and Hari Balachandran, et al, xe2x80x9cCorrelation of Logical Failures to a Suspect Process Stepxe2x80x9d, Proc. Int""l Test Conf. pp. 458-66 (1999).
In practice, the defect related faults in an IC manufacturing area occur in a dynamic manner, that is, the leading causes of failure fluctuate over time requiring that the failures must be continually monitored in order to know where defect reduction efforts should be focused to gain the greatest return. This requires an indicator that can quickly and continuously monitor the IC yield in order to direct the efforts appropriately. It is desirable that this indicator not increase the test time because the cost of testing ICs is often a significant contribution to the overall manufacturing cost.
Another characteristic of recent IC products is that their production lifetimes are decreasing. This means that yield enhancement information on a new product must be made available to a factory increasingly quickly.
It is an objective of this invention to use the statistical distribution of the electrical characteristics of failing parts, which will be referred to herein as a xe2x80x9csignaturexe2x80x9d, to predict the distribution of the processes that cause the failures. Using this information, the yield enhancement efforts can be focussed on the process steps for which improvements will provide the largest increase in yield.
It is a further objective of this invention to provide a method of quickly developing the correlations between physical layout and electrical failures needed to apply statistical failure distribution results to identification of the fault-causing defect distribution.
According to the present invention, a method is disclosed for utilizing information extracted from the physical design of an integrated circuit, usually referred to as the chip layout, in combination with the results of electrical tests of completed integrated circuits, to determine the relative fraction of failures caused by each layer in the IC manufacturing.
This can be divided into two operations: that of extracting information from the IC design and test program and operating on the information to put it in a form that it is useful for the defect origin prediction and that of applying the extracted knowledge to the results of test operations to identify the probability of the various layers causing the observed failures. The first operation must be performed only once per design/test set combination. The second operation may be performed repeatedly, e.g., once for each lot of ICs tested. Each operation will be discussed in turn.
The knowledge extraction operation begins by analyzing the chip layout layer by layer to identifying the regions in which a defect can cause a fault, i.e. an alteration of the circuit topology, and the relative likelihood that each fault will occur for a defect of a given size. (Each layer may be thought of as a conducting layer that may be incorrectly linked to another conductor to form a bridge fault or may be incorrectly broken to form a break fault.)
Once the faults are identified, the electrical output responses to a set of input stimuli are found. The set of responses to each fault is called a signature. In general, several faults may have the same signature. The fraction of the faults that respond with a unique signature to a set of input stimuli may be taken as a measure of the suitability of a stimuli set for diagnosis.
The relative signature distribution is obtained for each process layer. If there are i signatures and j process layers, the result can be represented as an i by j matrix. This matrix represents the knowledge base.
When a wafer or batch of wafers is tested with the stimuli, the results for the failing ICs may be arranged a distribution of signatures. This measured distribution must be composed of a linear combination of the signature distributions for the process layers where the distribution for each layer is weighted by the relative contribution of that layer to the failures observed. The measured signatures distribution can be inverted with help of the knowledge base matrix to yield the relative contribution of each process layer to the failures observed.